Field
The present disclosure generally relates to integrated circuits (ICs). More specifically, one aspect of the present disclosure relates to separate memory array and link error correction in a low power memory sub-system.
Background
Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell generally includes one transistor and one capacitor, which enables a high degree of integration. The capacitor can be either charged or discharged to store information as a corresponding bit value (e.g., ‘0’ or ‘1’). Because capacitors leak charge, the stored information eventually fades unless the capacitor charge is refreshed periodically. Due to the refresh requirement, DRAM is referred to as dynamic memory as opposed to SRAM and other static memory. The continuous refreshing of DRAM generally limits its use to computer main memory.
DRAM scaling continues to increase the total number of bits for each DRAM chip. Unfortunately, DRAM scaling increases the number of weak retention cells (e.g., cells that have a reduced retention time). Such cells involve additional refresh cycles to maintain the stored information. Advanced DRAM processes may suffer additional random bit refresh errors within a memory cell array due to the additional refresh cycles or other process variations. Some low power memories implement error correction codes (ECCs) to improve memory yield and reliability by applying ECCs to any random bit error in the memory cell array. ECC decoding and error correction, however, degrades memory performance due to an increased read access time. In addition, a memory link (e.g., interface) is not protected by the ECCs, and the overall memory reliability is insufficient for meeting high reliability and high performance system memory requirements.